1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a dynamic random access memory (DRAM) and its production method.
2. Description of the Prior Art
A semiconductor memory device of the prior art is disclosed, for example, in Japanese Laid-Open Patent Publication No. 61-208255.
FIG. 6 shows a memory cell of a prior art semiconductor memory device. The memory cell comprises an access transistor and a storage capacitor which are formed on a p-type silicon substrate 101 with a element isolation region 102. The access transistor comprises n-type diffused regions 103, a gate oxide film 104 formed on the p-type silicon substrate 101, and a gate electrode 105 formed on the gate oxide film 104. The storage capacitor 109 comprises a cell plate 106 formed over the p-type silicon substrate 101, a dielectric film 108 formed on the cell plate 106, a storage node 107 formed on the dielectric film 108 and connected to one of the n-type diffused regions 103. The storage node (storage electrode) 107 is formed by deposition of a conductive film and patterning the conductive film into the storage node by lithography and etching steps.
In the prior art semiconductor memory device, as the device elements becomes smaller, the lateral dimension L of the storage node 107 becomes smaller (distance between wiring patterns also decreases). However, to obtain a capacitance greater than some prescribed value, the storage capacitor 109 must have a larger surface area than some prescribed value. Therefore, to increase the surface area of the storage node 107, the height T of the storage node 107 should become larger. An increase in the height T of the storage node 107 results in an increase in the etching time in the dry etching process for patterning the storage node 107. This causes a narrowing effect of the pattern of the storage node 107. Further, as the lateral dimension L of the storage node 107 becomes smaller, an optical interference between adjacent cells occurs in the lithography process. This interference also has a narrowing effect of the pattern of the storage node 107. As described above, in the prior art semiconductor memory devices, it was difficult to form a large number of storage nodes 107 each having a large surface area.